In recent years, semiconductor memories such as flash memories are in the trend that large capacity and low cost data are introduced more and more rapidly. As the technology corresponding to novel attempt in introduction of such large capacity data, a multilevel flash memory utilizing the multilevel storage technology has been very popular in which a plurality of threshold voltages of a certain voltage level are set depending on the amount of charges accumulated in a charge storage layer of a memory chip and the data of two bits or more is stored.
According to discussion by the inventors of the present invention, the multilevel flash memory is provided with a structure that a memory cell array is divided, for example, to about four banks. Each bank has a structure that a sense latch is provided at the center thereof and data latches for storing write data are also provided in the vicinity of the two longer sides of the bank. The sense latches hold the information of the sense operation and the write object cells, while the data latches store write data.
The Japanese Unexamined Patent Publication No. Hei 02 (1990)-246087 is an example of the document which describes in details layout technology of peripheral circuits in the semiconductor memory of this type. This document specifically describes the layout technology of a main amplifier provided within a DRAM.
However, the inventors of the present invention have found the following problems in the layout technology of sense latch and data latch in the multilevel flash memory as described above.
Namely, such a multilevel flash memory is accompanied by a problem that the layout area required for the data latch becomes wide because the data of two bits or more is transferred with only one memory cell and the chip area also becomes large to hinder reduction in size of the flash memory because a degree of freedom of layout is also restricted.
An object of the present invention is to provide a nonvolatile semiconductor storage device which can remarkably reduce chip area without deterioration of data transfer rate by optimizing layout of data latch.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.